1. Field of the Invention
The present invention relates to a jitter suppression circuit for removing a jitter component contained in a synchronous reference clock signal which is supplied from a synchronization network to a phase locked loop (referred to hereinafter as PLL) circuit in a switching system to allow the PLL circuit to generate a clock signal in response thereto, so as to stabilize the clock signal from the PLL circuit.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a block diagram of a conventional PLL circuit, which is designated by the reference numeral 10. As shown in this drawing, the conventional PLL circuit 10 comprises a phase difference detector 11, a microprocessor 12, a digital/analog (referred to hereinafter as D/A) converter 13, a voltage controlled oscillator (referred to hereinafter as VCO) 14, and a frequency divider 15. The frequency divider 15 divides the frequency of a clock signal from the VCO 14 and supplies the frequency-divided clock signal to the phase difference detector 11, which also receives a synchronous reference clock signal which is supplied from a synchronization network through a reference clock receiver 1 and a band pass filter 2. The phase difference detector 11 then detects the phase difference between the frequency-divided clock signal and the synchronous reference clock signal in one unit of predetermined time thereby generating phase difference detect data. The microprocessor 12 scans the phase difference detect data from the phase difference detector 11 each predetermined unit of time and analyzes it. The microprocessor 12 then produces correction data based on the analyzed result and supplies the produced correction data to the D/A converter 13. The D/A converter 13 converts the correction data from the microprocessor 12 into a voltage for the control of the VCO 14. The VCO 14 controls a phase of its output clock signal in response to the control voltage from the D/A converter 13. The clock signal from the VCO 14 is also supplied to a switching system through a frequency synthesizer/distributor circuit 3.
In the above-mentioned conventional PLL circuit 10, the clock signal from the VCO 14 can be stabilized when the synchronous reference clock signal has no jitter component. However, in the case where a jitter component is contained in the synchronous reference clock signal, it has an effect on the control of the VCO 14, resulting in a variation in the phase of the clock signal from the VCO 14. In this case, the clock signal from the VCO 14 cannot be stabilized.